Epitaxial substrate for semiconductor device, semiconductor device, method of manufacturing epitaxial substrate for semiconductor device, and method of manufacturing semiconductor device

ABSTRACT

Provided is a semiconductor device of normally-off operation type having a low on-resistance. An epitaxial substrate for it includes: a base substrate; a channel layer made of a first group-III nitride having a composition of In x1 Al y1 Ga z1 N at least containing Al and Ga and x1=0 and 0≦y1≦0.3; and a barrier layer made of a second group-III nitride having a composition of In x2 Al y2 Ga z2 N at least containing In and Al. The composition of the second group-III nitride is, in a ternary phase diagram for InN, AlN, and GaN, in a certain range that is determined in accordance with the composition of the first group-III nitride. The barrier layer has a thickness of 3 nm or less. A low-crystallinity insulating layer is further formed on the barrier layer. The low-crystallinity insulating layer is made of silicon nitride and has a thickness of 3 nm or less.

TECHNICAL FIELD

The present invention relates to an epitaxial substrate having amultilayer structure made of a group-III nitride semiconductor, andparticularly to an epitaxial substrate having a multilayer structure foruse in a semiconductor device, to a method of manufacturing it, and tothe semiconductor device.

BACKGROUND ART

A group-III nitride semiconductor is attracting attention as asemiconductor material for a next-generation high-frequency/high-powerdevice, because the nitride semiconductor has a high breakdown electricfield and a high saturation electron velocity. For example, an HEMT(high electron mobility transistor) device in which a barrier layer madeof AlGaN and a channel layer made of GaN are laminated takes advantageof the feature that causes a high-concentration two-dimensional electrongas (2DEG) to occur in a lamination interface (hetero interface) due tothe large polarization effect (a spontaneous polarization effect and apiezo polarization effect) specific to a nitride material (for example,see Non-Patent Document 1).

In some cases, a single crystal (a different kind single crystal) havinga composition different from that of a group-III nitride, such assilicon and SiC, is used as a base substrate of an HEMT-devicesubstrate. In this case, a buffer layer such as a strained-superlatticelayer or a low-temperature growth buffer layer is generally formed as aninitially-grown layer on the base substrate. Accordingly, aconfiguration in which a barrier layer, a channel layer, and a bufferlayer are epitaxially formed on a base substrate is the most basicconfiguration of the HEMT-device substrate including a base substratemade of a different kind single crystal. Additionally, a spacer layerhaving a thickness of about 1 nm may be sometimes provided between thebarrier layer and the channel layer, for the purpose of facilitating aspatial confinement of the two-dimensional electron gas. The spacerlayer is made of, for example, AlN. Moreover, a cap layer made of, forexample, an n-type GaN layer or a superlattice layer may be sometimesformed on the barrier layer, for the purpose of controlling the energylevel at the most superficial surface of the HEMT-device substrate andimproving contact characteristics of contact with an electrode.

In order to put into practical use the HEMT device or the HEMT-devicesubstrate that is a multilayer structure used for preparation of theHEMT device, various problems have to be solved including problemsconcerning improvement of the performance such as increasing the powerdensity and efficiency, problems concerning improvement of thefunctionality such as a normally-off operation, fundamental problemsconcerning a high reliability and a price reduction, and the like.Active efforts are made on each of the problems.

For example, it is known that, in a case where a nitride HEMT device hasthe most general configuration in which a channel layer is made of GaNand a barrier layer is made of AlGaN, the concentration of atwo-dimensional electron gas existing in an HEMT-device substrateincreases as the AlN mole fraction in AlGaN of the barrier layerincreases (for example, see Non-Patent Document 2). If the concentrationof the two-dimensional electron gas can be considerably increased, thecontrollable current density of the HEMT device, that is, the powerdensity that can be handled, would be considerably improved.

Also attracting attention is an HEMT device having a structure withreduced strain, such as an HEMT device in which a channel layer is madeof GaN and a barrier layer is made of InAlN, in which the dependence ona piezo polarization effect is small and almost only a spontaneouspolarization is used to generate a two-dimensional electron gas with ahigh concentration (for example, see Non-Patent Document 3).

As for the normally-off operation, from the viewpoint of fail-safe, itis generally desirable that an electronic device, and particularly apower semiconductor device that handles a power control, performs anormally-off operation, that is, an operation that blocks conductionwhen no electrical signal is not inputted from the outside. On the otherhand, an HEMT device made of a group-III nitride semiconductor is adevice that uses a two-dimensional electron gas generated at a heterointerface as described above. Therefore, in an normally-on operationrather than the normally-off operation, the HEMT device originallyexerts excellent conduction characteristics, that is, a lowon-resistance. As a method for achieving the normally-off operation ofthe HEMT device made of a group-III nitride semiconductor, the followingmethods are known.

As for a nitride HEMT device of Schottky gate structure type including achannel layer made of GaN and a barrier layer made of AlGaN, forexample, there are known: (1) a method in which the thickness of AlGaNbarrier layer is reduced so that a gate threshold voltage (hereinafter,also referred to simply as a threshold voltage) is shifted in a positivedirection, and thereby the normally-off is achieved (for example, seeNon-Patent Document 4); and (2) a method in which recess etching isperformed only in a portion immediately below a gate electrode (forexample, see Non-Patent Document 5).

Alternatively, there are also known (3) a method in which, instead of aSchottky junction, a MIS (metal-insulator-semiconductor) structure withinterposition of an insulating layer is adopted in an HEMT device ofrecess gate structure type (for example, see Non-Patent Document 6 andNon-Patent Document 7); and (4) a method in which an HEMT device havingan inverted channel structure is prepared using an MIS gate structure(for example, see Non-Patent Document 8).

Moreover, there is also known (5) a method in which a channel layer ismade of AlGaN whose Al mole fraction in all the group-III elements is0.3 while a barrier layer is made of InAlGaN whose composition is in apredetermined composition range, to thereby achieve an HEMT devicehaving a two-dimensional electron gas concentration of 2×10¹³/cm² orhigher and capable of the normally-off operation (for example, seePatent Document 1).

The above-described methods for achieving the normally-off operation inthe HEMT device, except the method (5), involves problems that amanufacturing process is troublesome and that a sufficiently-lowon-resistance is not obtained.

For example, in a case of the method (1), the reduction in the thicknessof the barrier layer lowers the two-dimensional electron gasconcentration. As a result, a low on-resistance, which is the originalfeature of the nitride HEMT device, cannot be obtained. The reasontherefor is considered as follows. As the thickness of the barrier layerdecreases, the distance between a channel portion and a surface of thebarrier layer decreases. As a result, the potential of a surface levelcontributes to generation of electric charges, or a piezo polarizationeffect is reduced.

In the method (2), the adding of recess processing makes the processtroublesome. To ensure the reproducibility in a device manufacturingprocess (to enable a device having a certain quality to be stablymanufactured), a high accuracy of the recess processing is demanded.

The methods (1) and (2) are directed to an HEMT device of Schottky gatestructure type, in which an upper limit of a positive voltage that canbe applied to the gate electrode is determined by the height of aSchottky barrier. When a gate positive voltage is set to be about 1.5Vor more, it is difficult to ensure a large drain current whilesuppressing a gate leakage current. On the other hand, the HEMT devicehas a feature that, when the HEMT device is designed to have a widerange of gate voltage application, a drain current thereof is increased.For example, in a case where the threshold voltage is −3V, the gatevoltage range spans 4.5V, that is, from −3V to about +1.5V. However, ina case of the HEMT device designed such that the threshold voltagethereof is a positive value (>0V) by reducing the thickness of itsbarrier layer, the gate voltage range spans, at most, about 1.5V. Inthis case, while a maximum drain current (on-current) of the former isabout 0.8 A/mm, that of the latter is about 0.4 A/mm or less. Such areduction in an on-current is more noticeable as the shift of thethreshold voltage to the positive side is larger. Accordingly, when thenormally-off operation is performed in a nitride HEMT device having aSchottky gate, a problem arises that a wide gate voltage range is notensured and therefore a large drain current does not flow (theon-resistance cannot be lowered), resulting in a failure to obtain goodconduction characteristics.

In the method (3), the recess processing and the insulating filmformation process are added, which makes the process troublesome. Toensure the reproducibility in a device manufacturing process (to enablea device having a certain quality to be stably manufactured), a highaccuracy of the recess processing is demanded.

The method (4) requires the step of forming the MIS gate structure.Moreover, the electron mobility in the inverted MIS channel structure islow, namely, 200 cm²/Vs or less. Therefore, even when the normally-offoperation is achieved, the performance of the HEMT device itself isdegraded.

PRIOR-ART DOCUMENTS Patent Documents

-   Patent Document 1: International Patent Publication No. 2009/119357

Non-Patent Documents

-   Non-Patent Document 1: “Highly Reliable 250 W High Electron Mobility    Transistor Power Amplifier”, TOSHIHIDE KIKKAWA, Jpn. J. Appl. Phys.    44, (2005), pp. 4896-4901.-   Non-Patent Document 2: “Gallium Nitride Based High Power    Heterojuncion Field Effect Transistors: process Development and    Present Status at USCB”, Stacia Keller, Yi-Feng Wu, Giacinta Parish,    Naiqian Ziang, Jane J. Xu, Bernd P. Keller, Steven P. DenBaars, and    Umesh K. Mishra, IEEE Trans. Electron Devices 48, (2001), pp.    552-559.-   Non-Patent Document 3: “Can InAlN/GaN be an alternative to high    power/high temperature AlGaN/GaN devices?”, F. Medjdoub, J.-F.    Carlin, M. Gonschorek, E. Feltin, M. A. Py, D. Ducatteau, C.    Gaquiere, N. Grandjean, and E. Kohn, IEEE IEDM Tech. Digest in IEEE    IEDM 2006, pp. 673-676.-   Non-Patent Document 4: “Non-Recessed-Gate Enhancement-Mode AlGaN/GaN    High Electron Mobility Transistors with High RF Performance”, Akira    ENDOH, Yoshimi YAMASHITA, Keiji IKEDA, Masataka HIGASHIWAKI, Kohki    HIKOSAKA, Toshiaki MATSUI, Satoshi HIYAMIZU and Takachi MIMURA,    Japanese Journal of Applied Physics Vol. 43, No. 413, 2004, pp.    2255-2258.-   Non-Patent Document 5: “Recessed-Gate Structure Approach Toward    Normally Off High-Voltage AlGaN/GaN HEMT for Power Electronics    Applications”, Wataru Saito, Yoshiharu Takada, Masahiko Kuraguchi,    Kunio Tsuda, and Ichiro Omura, IEEE Trans. Electron Devices, 53,    (2006), pp. 356-362.-   Non-Patent Document 6: “Enhancement-Mode GaN MIS-HEMTs With    n-GaN/i-AlN/n-GaN Triple Cap Layer and High-κ Gate Dielectrics”,    Masahiro Kanamura, Toshihiro Ohki, Toshihide Kikkawa, Kenji    Imanishi, Tadahiro Imada, Atsushi Yamada, and Naoki Hara, IEEE    Electron Device Lett., 31, (2010), pp. 189-191.-   Non-Patent Document 7: “A Normally-off GaN FET with High Threshold    Voltage Uniformity Using A Novel Piezo Neutralization Technique”, K.    Ota, K. Endo, Y. Okamoto, Y. Ando, H. Miyamoto, and H. Shimawaki,    IEEE IEDM2009 Tech. Digest, pp. 1-4.-   Non-Patent Document 8: “Over 100 A Operation normally-off AlGaN/GaN    hybrid MOS-HFET on Si substrate with high-breakdown voltage”,    Hiroshi Kambayashi, Yoshihiro Satoh, Shinya Oomoto, Takuya Kokawa,    Takehiro Nomura, Sadahiro Kato, Tat-sing Pawl Chow, Solid-State    Electronics 54, (2010), pp. 660-664.

SUMMARY OF THE INVENTION

The present invention has been made in view of the problems describedabove, and an object of the present invention is to provide asemiconductor device of normally-off operation type having a lowon-resistance, and to provide a method for preparing the semiconductordevice without any complicated step.

To solve the problems described above, in a first aspect of the presentinvention, an epitaxial substrate for semiconductor device includes: abase substrate; a channel layer made of a first group-III nitride havinga composition of In_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1) that contains atleast Al and Ga; and a barrier layer made of a second group-III nitridehaving a composition of In_(x2)Al_(y2)Ga_(x2)N (x2+y2+z2=1) thatcontains at least In and Al. The composition of the first group-IIInitride is in a range determined by x1=0 and 0≦y1≦0.3. The compositionof the second group-III nitride is, in a ternary phase diagram for InN,AlN, and GaN, in a range that is enclosed by straight lines representedby the following expressions and that is determined in accordance withthe composition of the first group-III nitride. The barrier layer has athickness of 3 nm or less. A low-crystallinity insulating layer isformed on the barrier layer, the low-crystallinity insulating layerbeing made of silicon nitride and having a thickness of 3 nm or less.

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z2=0

In a second aspect of the present invention, the epitaxial substrate forsemiconductor device according to the first aspect further includes asub insulating layer provided between the barrier layer and thelow-crystallinity insulating layer, the sub insulating layer being madeof a group-III nitride with insulating properties and having a thicknessof 2.5 nm or less.

In a third aspect of the present invention, in the epitaxial substratefor semiconductor device according to the second aspect, the subinsulating layer is made of AlN.

In a fourth aspect of the present invention, the epitaxial substrate forsemiconductor device according to any of the first or second aspectfurther includes a spacer layer provided between the channel layer andthe barrier layer, the spacer layer being made of a third group-IIInitride having a composition of In_(x3)Al_(y3)Ga_(z3)N (x3+y3+z3=1) thatcontains at least Al and that has higher band gap energy than that ofthe barrier layer. A total thickness of the spacer layer and the barrierlayer is 5 nm or less.

In a fifth aspect of the present invention, in the epitaxial substratefor semiconductor device according to the fourth aspect, the spacerlayer is made of AlN.

In a sixth aspect of the present invention, a semiconductor deviceincludes: a base substrate; a channel layer made of a first group-IIInitride having a composition of In_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1) thatcontains at least Al and Ga; and a barrier layer made of a secondgroup-III nitride having a composition of In_(x2)Al_(y2)Ga_(z2)N(x2+y2+z2=1) that contains at least In and Al. The composition of thefirst group-III nitride is in a range determined by x1=0 and 0≦y1≦0.3.The composition of the second group-III nitride is, in a ternary phasediagram for InN, AlN, and GaN, in a range that is enclosed by straightlines represented by the following expressions and that is determined inaccordance with the composition of the first group-III nitride. Thebarrier layer has a thickness of 3 nm or less. A low-crystallinityinsulating layer is formed on the barrier layer, the low-crystallinityinsulating layer being made of silicon nitride and having a thickness of3 nm or less. A source electrode and a drain electrode are formed on thelow-crystallinity insulating layer with an ohmic junction and a gateelectrode is formed on the low-crystallinity insulating layer with aSchottky junction.

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z2=0

In a seventh aspect of the present invention, a method of manufacturingan epitaxial substrate for semiconductor device includes: a channellayer formation step of epitaxially forming a channel layer on a basesubstrate, the channel layer being made of a first group-III nitridehaving a composition of In_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1) thatcontains at least Al and Ga; a barrier layer formation step ofepitaxially forming a barrier layer on the channel layer, the harrierlayer being made of a second group-III nitride having a composition ofIn_(x2)Al_(y2)Ga_(z2)N (x2+y2+z2=1) that contains at least In and Al;and a main insulating layer formation step of forming a main insulatinglayer on the barrier layer, the main insulating layer being made ofsilicon nitride. In the channel layer formation step, the composition ofthe first group-III nitride is selected from a range determined by x1=0and 0≦y1≦0.3. In the barrier layer formation step: the composition ofthe second group-III nitride is selected from a range that is enclosedby straight lines represented by the following expressions and that isdetermined in accordance with the composition of the first group-IIInitride in a ternary phase diagram for InN, AlN, and GaN; and thebarrier layer is formed with a thickness of 3 nm or less. In the maininsulating layer formation step, the main insulating layer is formedwith a thickness of 3 nm or less at a formation temperature of 750° C.or more and 850° C. or less.

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z2=0.4z2=0

In an eighth aspect of the present invention, the method ofmanufacturing an epitaxial substrate for semiconductor device accordingto the seventh aspect further includes a sub insulating layer formationstep of forming a sub insulating layer on the barrier layer, the subinsulating layer being made of a group-III nitride with insulatingproperties and having a thickness of 2.5 nm or less. The main insulatinglayer is formed on the sub insulating layer.

In a ninth aspect of the present invention, in the method ofmanufacturing an epitaxial substrate for semiconductor device accordingto the eighth aspect, the sub insulating layer is made of AlN.

In a tenth aspect of the present invention, the method of manufacturingan epitaxial substrate for semiconductor device according to the seventhor eighth aspect further includes a spacer layer formation step offorming a spacer layer on the channel layer, the spacer layer being madeof a third group-III nitride having a composition ofIn_(x3)Al_(y3)Ga_(z3)N (x3+y3+z3=1) that contains at least Al and thathas higher band gap energy than that of the barrier layer. The barrierlayer is formed on the spacer layer.

In an eleventh aspect of the present invention, in the method ofmanufacturing an epitaxial substrate for semiconductor device accordingto the tenth aspect, the spacer layer is made of AlN.

In a twelfth aspect of the present invention, in the method ofmanufacturing an epitaxial substrate for semiconductor device accordingto the seventh or eighth aspect: a temperature T1(° C.) at which thechannel layer is formed is determined within a range of 950° C.≦T1≦1250°C.; and a temperature T2(° C.) at which the barrier layer is formed isdetermined within a range of 800−667·x2(° C.)≦T2≦860−667·x2(° C.) and600° C.≦T2≦850° C., the range being determined in accordance with an InNmole fraction x2 in the second group-ill nitride.

In a thirteenth aspect of the present invention, a method ofmanufacturing a semiconductor device includes the steps of: preparing anepitaxial substrate through the method of manufacturing an epitaxialsubstrate for semiconductor device according to any of claims 7 to 12;forming a source electrode and a drain electrode on the main insulatinglayer of the epitaxial substrate, with an ohmic junction; performing aheat treatment on the epitaxial substrate having the source electrodeand the drain electrode formed thereon; and forming a gate electrode onthe main insulating layer, with a Schottky junction.

In the first, fifth, and seventh to twelfth aspects of the presentinvention, an epitaxial substrate having a high two-dimensional electronconcentration and a low sheet resistance is achieved. Forming asemiconductor device by using such an epitaxial substrate achieves asemiconductor device of normally-off operation type having a lowon-resistance in which a gate threshold voltage has a positive value andan upper limit of a gate voltage is high.

Particularly, in the second, third, eighth, and ninth aspects, asemiconductor device of normally-off operation type in which a gateleakage current is further reduced is achieved.

Particularly, in the fourth, fifth, tenth, and eleventh aspects, asemiconductor device of normally-off operation type in which themobility of a two-dimensional electron gas is high is achieved.

Particularly, in the twelfth aspect, by determining the temperature atwhich the barrier layer is formed in accordance with a targetcomposition of the barrier layer, the barrier layer having such a targetcomposition can be surely formed.

In the sixth and thirteenth aspects, the semiconductor device can beprepared by using an epitaxial substrate having a high two-dimensionalelectron concentration and a low sheet resistance. Accordingly, asemiconductor device of normally-off operation type having a lowon-resistance in which a gate threshold voltage has a positive value andan upper limit of a gate voltage is high can be achieved withoutperforming a troublesome step of forming a recess gate structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 A schematic cross-sectional view showing an outline configurationof an HEMT device 20 that is one aspect of a semiconductor deviceaccording to an embodiment of the present invention.

FIG. 2 A ternary phase diagram showing a composition range of a barrierlayer 5 in a case where a channel layer is made of GaN.

FIG. 3 A ternary phase diagram showing a composition range of thebarrier layer 5 in a case where the channel layer is made ofAl_(0.1)Ga_(0.9)N.

FIG. 4 A ternary phase diagram showing a composition range of thebarrier layer 5 in a case where the channel layer is made ofAl_(0.2)Ga_(0.8)N.

FIG. 5 A ternary phase diagram showing a composition range of thebarrier layer 5 in a case where the channel layer is made ofAl_(0.3)Ga_(0.7)N.

FIG. 6 A diagram for explaining a method for setting a temperature rangeof a barrier layer formation temperature T2.

EMBODIMENT FOR CARRYING OUT THE INVENTION

<Configuration of HEMT Device>

FIG. 1 is a schematic cross-sectional view showing an outlineconfiguration of an HEMT device 20 that is one aspect of a semiconductordevice according to an embodiment of the present invention. Roughly, theHEMT device 20 has a configuration in which a source electrode 7, adrain electrode 8, and a gate electrode 9 are arranged on an epitaxialsubstrate 10. More specifically, the epitaxial substrate 10 has aconfiguration in which a base substrate 1, a buffer layer 2, a channellayer 3, a spacer layer 4, and a barrier layer 5 are laminated such thata (0001) crystal plane is substantially in parallel with a substratesurface. Additionally, an insulating layer 6 is formed on the barrierlayer 5. In the HEMT device 20, the source electrode 7, the drainelectrode 8, and the gate electrode 9 are formed on the insulating layer6 of the epitaxial substrate 10. The thickness ratio among the layersshown in FIG. 1 does not reflect the actual ratio. In one preferredexample, all of the buffer layer 2, the channel layer 3, the spacerlayer 4, the barrier layer 5, and the insulating layer 6 are epitaxiallyformed through a MOCVD process (Metal Organic Chemical Vapor Deposition)(details will be described later).

The following description is directed to a case where the MOCVD processis used for the formation of each layer. However, a method appropriatelyselected from other epitaxial growth processes including vapordeposition processes and liquid phase deposition processes such as MBE,HVPE, and LPE may be adopted, or different growth processes may beadopted in combination, as long as the method can form each of thelayers with good crystallinity.

No particular limitation is put on the base substrate 1, as long as thebase substrate 1 allows a nitride semiconductor layer with goodcrystallinity to be formed thereon. In one preferable example, a singlecrystal 6H—SiC substrate is used. However, a substrate made of sapphire,Si, GaAs, spinel, MgO, ZnO, ferrite, or the like, may be adopted.

The buffer layer 2 is a layer made of AlN, and formed with a thicknessof about several hundreds of nm, for the purpose of obtaining goodcrystal quality of the channel layer 3, the spacer layer 4, the barrierlayer 5, and the insulating layer 6 which will be formed on the bufferlayer 2. In one preferable example, the buffer layer 2 is formed with athickness of 200 nm.

The channel layer 3 is a layer made of a group-III nitride having acomposition of In_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1), and formed with athickness of about several μm. In this embodiment, the channel layer 3is formed such that its composition range satisfies x1=0 and 0≦y1≦0.3.In a case of 0.3≦y1≦1, the crystallinity of the channel layer 3 itselfis significantly degraded, which makes it difficult to obtain anepitaxial substrate 10, and thus an HEMT device 20, having goodelectrical characteristics.

On the other hand, the barrier layer 5 is a layer made of a group-IIInitride having a composition of In_(x2)Al_(y2)Ga_(z2)N (here,x2+y2+z2=1), and formed with a thickness of 3 nm or less. Thecomposition of the barrier layer 5 is selected from a predeterminedcomposition range in a ternary phase diagram for three components ofInN, AlN, and GaN, as will be described later.

Moreover, the spacer layer 4 is provided between the channel layer 3 andthe barrier layer 5. The spacer layer 4 is a layer made of a group-IIInitride having a composition of In_(x3)Al_(y3)Ga_(z3)N (x3+y3+z3=1),containing at least Al (that satisfies y3>0), and having a band gaplarger than the band gap of the barrier layer 5. The spacer layer 4 isformed with a thickness of 0.5 nm to 1.5 nm. Preferably, the spacerlayer 4 is formed so as to satisfy x3=0 and 0≦z3≦0.05. In such a case,an alloy scattering effect is suppressed, and the concentration and themobility of a two-dimensional electron gas are improved. Morepreferably, the spacer layer 4 is made of AlN.

In the epitaxial substrate 10 having such a layer configuration, atwo-dimensional electron gas region 3 e, in which the two-dimensionalelectron gas exists with a high concentration, is formed at an interfacebetween the channel layer 3 and the spacer layer 4 (more specifically,in a portion of the channel layer 3 near this interface).

However, it is not essential that the spacer layer 4 is provided in theepitaxial substrate 10. It may be also acceptable that the barrier layer5 is formed directly on the channel layer 3. In this case, thetwo-dimensional electron gas region 3 e is formed at an interfacebetween the channel layer 3 and the barrier layer 5.

In order to successfully generate the two-dimensional electron gas inthe two-dimensional electron gas region 3 e, an interface between thechannel layer 3 and the spacer layer 4 immediately above the channellayer 3 or an interface between the channel layer 3 and the barrierlayer 5 is formed such that the mean roughness of the interface is inthe range from 0.1 nm to 3 nm. Additionally, a surface of the spacerlayer 4 or the barrier layer 5 is formed such that the mean squareroughness of the surface is in the range from 0.1 nm to 3 nm. Althoughit may be also acceptable to form a flat interface beyond theabove-mentioned range, this is not practical from the viewpoint ofcosts, the production yield, and the like. Preferably, theabove-mentioned mean roughness is in the range from 0.1 nm to 1 nm andthe above-mentioned mean square roughness is in the range from 0.1 nm to1 nm. In such a case, an effect of confinement of the two-dimensionalelectron gas is further enhanced, to generate the two-dimensionalelectron gas with a higher concentration.

The insulating layer 6 is a layer provided for the purpose of improvingthe characteristics of the epitaxial substrate 10 and the HEMT device20. The insulating layer 6 includes a main insulating layer 6 a servingas an uppermost layer of the epitaxial substrate 10, and a subinsulating layer 6 b interposed between the barrier layer 5 and the maininsulating layer 6 a.

The main insulating layer 6 a is a layer made of silicon nitride (suchas SiN), and formed with a thickness of 3 nm or less. The maininsulating layer 6 a is formed as a layer having a lower crystallinitythan that of the ordinary insulating layer. This is achieved by, forexample, setting a formation temperature at which the main insulatinglayer 6 a is formed (in a case where the MOCVD process is adopted, thetemperature of a susceptor of an MOCVD apparatus mentioned above) to be750° C. to 850° C., which is lower than an ordinary formationtemperature (about 1000° C. to 1200° C.) adopted in a case where asilicon nitride layer is provided as the insulating layer. The maininsulating layer 6 a formed in this manner will be also referred to as alow-crystallinity insulating layer. Forming the low-crystallinityinsulating layer as the main insulating layer 6 a exerts an effect insuppression of a contact resistance of the HEMT device 20. Detailsthereof will be described later.

The sub insulating layer 6 b is a layer made of a group-III nitridehaving insulating properties, and formed with a thickness of 2.5 nm orless. The sub insulating layer 6 b is laminated such that a (0001)crystal plane of the barrier layer 5 is substantially in parallel withthe substrate surface. Preferably, the sub insulating layer 6 b is madeof AlN, and formed with a thickness of 2 nm or less. However, it is notessential that the sub insulating layer 6 b is provided in the epitaxialsubstrate 10. It may be also acceptable that only the main insulatinglayer 6 a is formed as the insulating layer 6 on the barrier layer 5.

Each of the source electrode 7 and the drain electrode 8 is a multilayermetal electrode whose metal layer has a thickness of about more than tennm to one hundred and several tens of nm. Each of the source electrode 7and the drain electrode 8 has an ohmic contact with the insulating layer6. The source electrode 7 and the drain electrode 8 may be formed of ametal material that provides a good ohmic contact relative to theepitaxial substrate 10 (relative to the insulating layer 6). It ispreferable that multilayer metal electrodes made of Ti/Al/Ni/Au areformed as the source electrode 7 and the drain electrode 8. However,this is not limiting. For example, a multilayer metal electrode made ofTi/Al/Pt/Au or Ti/Al may be formed. The formation of the sourceelectrode 7 and the drain electrode 8 can be implemented through aphotolithography process and a vacuum vapor deposition process.

On the other hand, the gate electrode 9 is a single-layer or multilayermetal electrode in which one or more metal layers are formed with athickness of more than ten nm to one hundred and several tens of nm. Thegate electrode 9 has a Schottky contact with the barrier layer 5 withinterposition of the insulating layer 6. It is preferable that the gateelectrode 9 is made of as a material, a metal having a high workfunction, such as Pd, Pt, Ni, and Au. Alternatively, it may be possibleto form, as the gate electrode 9, a multilayer metal film consisted ofsome of the above-mentioned metals or concisted of some of the metalsand Al, for example. The formation of the gate electrode 9 can beimplemented through a photolithography process and a vacuum vapordeposition process.

Since the insulating layer 6 is interposed between the gate electrode 9and the barrier layer 5, the HEMT device 20 can be considered as havingan MIS gate structure.

<Relationship Between Device Characteristics and Compositions of ChannelLayer and Barrier Layer>

In this embodiment, as disclosed in Patent Document 1, the compositionof the barrier layer 5 is selected from a range that is enclosed by fourstraight lines represented by the following expressions in a ternaryphase diagram for three components of InN, AlN, and GaN. Thereby, atwo-dimensional electron gas concentration in the two-dimensionalelectron gas region 3 e of the epitaxial substrate 10 is 2×10¹³/cm² ormore, and a threshold voltage of the HEMT device 20 is more than 0V.Thus, satisfying this composition range enables a high two-dimensionalelectron gas concentration to be maintained and the HEMT device 20capable of a normally-off operation to be achieved.

$\begin{matrix}{{x\; 2} = {\frac{{y\; 2} - \left( {0.27 + {0.5{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.73 - {0.5{yl}}} \right)}{2.78}}}} & (1) \\{{x\; 2} = {\frac{{y\; 2} - \left( {0.4 + {0.6{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.6 - {0.6{yl}}} \right)}{2.78}}}} & (2)\end{matrix}$z2=0.4  (3)

z2=0  (4)

The expressions (1) and (2) contain, as a variable, the composition ofthe channel layer 3 (to be specific, the value of y1 in a case of x1=0).This means that the composition of the barrier layer 5 that allowsachievement of both a high two-dimensional electron gas concentration of2×10¹³/cm² or more and a threshold voltage more than 0V is determined inaccordance with the composition of the channel layer 3.

In FIGS. 2, 3, 4, and 5, the composition range of the barrier layer 5indicated by the expressions (1) to (4) is shown on ternary phasediagrams for three components of InN, AlN, and GaN. In each of the FIGS,the composition of the channel layer 3 is as follows.

FIG. 2: GaN (x1=y1=0, z=1);

FIG. 3: Al_(0.1)Ga_(0.9)N (x1=0, y1=0.1, z1=0.9);

FIG. 4: Al_(0.2)Ga_(0.8)N (x1=0, y1=0.2, z1=0.8);

FIG. 5: Al_(0.3)Ga_(0.7)N (x1=0, y1=0.3, z1=0.7).

Setting the composition ranges of the channel layer 3 and the barrierlayer 5 in the above-described manner does not exclude that the channellayer 3 and the barrier layer 5 contain impurities. For example, thechannel layer 3 and the barrier layer 5 may contain oxygen atoms withina concentration range from 0.0005 at % (1×10¹⁷/cm³) or more to 0.05 at %(1×10¹⁹/cm³) or less, or may contain carbon atoms within a concentrationrange from 0.0010 at % (2×10¹⁷/cm³) or more to 0.05 at % (1×10¹⁹/cm³) orless. Although the concentrations of oxygen atoms and carbon atoms maybe below their respective lower limit values within the aforementionedranges, this is not practical from the viewpoint of costs, theproduction yield, and the like. On the other hand, the concentrations ofoxygen atoms and carbon atoms exceeding their respective upper limitvalues within the aforementioned ranges are not preferable, because thecrystallinity of each layer is degraded to an extent that causesdegradation of device characteristics.

<Spacer Layer>

The spacer layer 4 is a layer provided for the purpose of enhancing theeffect of confinement of the two-dimensional electron gas in thetwo-dimensional electron gas region 3 e. In a case where the spacerlayer 4 is provided, the mobility of the two-dimensional electron gas inthe HEMT device 20 is improved. For example, the HEMT device 20 notincluding the spacer layer 4 has a mobility of about 300 to 400 cm²/Vs,while the HEMT device 20 including the spacer layer 4 has a mobility ofabout 1000 to 1400 cm²/Vs.

However, when the spacer layer 4 is formed with a thickness smaller than0.5 nm, the formation is the layer is insufficient, and thus the effectof confinement of the two-dimensional electron gas is not sufficientlyobtained. On the other hand, when the spacer layer 4 is formed with athickness greater than 1.5 nm, the film quality of the spacer layer 4itself is degraded due to an internal stress, and thus sufficientimprovement in the mobility cannot be expected.

When the channel layer 3 contains oxygen atoms or nitrogen atoms withinthe above-mentioned concentration range, the spacer layer 4 alsocontains them with the same concentration range.

<Method of Manufacturing Epitaxial Substrate and HEMT Device>

Next, a description will be given to a method for preparing theepitaxial substrate 10 and the HEMT device 20 having the above-describedconfiguration.

In the following, a case where many HEMT devices 20 are simultaneouslyprepared from one base substrate 1 (a case of producing a large numberof devices) will be described.

The preparation of the epitaxial substrate 10 can be performed by usinga known MOCVD apparatus. More specifically, an MOCVD apparatus is usedthat is configured to feed, into a reactor, a source gas (TMI, TMA, TMG)of an organic metal (MO) of In, Al, Ga, a silane gas that is a sourcegas of Si, an ammonia gas, a hydrogen gas, and a nitrogen gas.

Firstly, for example, a (0001)-oriented 6H—SiC substrate having adiameter of two inches is prepared as the base substrate 1, and thisbase substrate 1 is placed on a susceptor provided in a reactor of theMOCVD apparatus. The inside of the reactor is vacuumed, and then, anatmosphere in a hydrogen/nitrogen mixed flow state is created while apressure inside the reactor is kept at a predetermined value in therange from 5 kPa to 50 kPa. In this condition, the susceptor is heatedto thereby raise the temperature of the substrate.

When the temperature of the susceptor reaches a predeterminedtemperature in the range from 950° C. to 1250° C. (for example, 1050°C.), which is a buffer layer formation temperature, an Al source gas anda NH₃ gas are introduced into the reactor, and thereby an AlN layerserving as the buffer layer 2 is formed.

After the formation of the AlN layer, the temperature of the susceptoris kept at a predetermined channel layer formation temperature T1(° C.),and a metal organic source gas and an ammonia gas are introduced intothe reactor in accordance with the composition of the channel layer 3,and thereby an In_(x1)Al_(y1)Ga_(z1)N layer (x1=0, 0≦y1≦0.3) serving asthe channel layer 3 is formed. Here, the channel layer formationtemperature T1 is a value determined in a temperature range of 950°C.≦T1≦1250° C. in accordance with a value of an AlN mole fraction y1 inthe channel layer 3. No particular limitation is put on the pressure inthe reactor at a time when the channel layer 3 is formed. A pressure canbe appropriately selected from the range from 10 kPa to an atmosphericpressure (100 kPa).

After the formation of the In_(x1)Al_(y1)Ga_(z1)N layer, a nitrogen gasatmosphere inside the reactor is maintained while the temperature of thesusceptor is kept. The pressure in the reactor is set to be 10 kPa, andthen a metal organic source gas and an ammonia gas are introduced intothe reactor, so that an In_(x3)Al_(y3)Ga_(z3)N layer serving as thespacer layer 4 is formed with a predetermined thickness.

As will be described later, when the barrier layer 5 is formed, thetemperature of the susceptor is set to be 800° C. or less. Therefore, itis necessary to lower the temperature of the susceptor after theformation of the spacer layer 4. In a case where no spacer layer 4 isprovided, the surface of the channel layer 3 is exposed during thelowering of the temperature, which may cause the surface to be etched byan atmosphere gas. On the other hand, in a case where the spacer layer 4is formed at a temperature substantially equal to the channel layerformation temperature T1, the temperature of the susceptor is loweredafter the formation of the spacer layer 4. As a result, the spacer layer4 acts as a protection layer that protects the surface of the channellayer 3. This would also contribute to improvement in the mobility ofthe two-dimensional electron gas.

After the formation of the In_(x3)Al_(y3)Ga_(z3)N layer, the temperatureof the susceptor is kept at a predetermined barrier layer formationtemperature T2(° C.), and a nitrogen gas atmosphere is created withinthe reactor. At this time, the pressure inside the reactor is kept at apredetermined value (for example, 10 kPa) in the range from 1 kPa to 30kPa. Here, setting the pressure inside the reactor to be a predeterminedvalue in the range from 1 kPa to 20 kPa achieves an HEMT device 20having a low ohmic contact resistance and a less gate leakage current(having good Schottky contact characteristics). This effect derives fromthe fact that lowering the pressure in the reactor increases the surfaceflatness of the barrier layer 5.

Then, an ammonia gas and a metal organic source gas with a flow ratio inaccordance with the composition of the barrier layer 5 are introducedinto the reactor such that the so-called V/III ratio has a predeterminedvalue of 3000 or more and 20000 or less is obtained. Thus, anIn_(x2)Al_(y2)Ga_(z2)N layer serving as the barrier layer 5 is formedwith a predetermined thickness. The In_(x2)Al_(y2)Ga_(z2)N layer isformed so as to having a composition that satisfies the expressions (1)to (4). A preferable range of the rate of growth of the barrier layer 5is 0.01 to 0.1 μm/h.

In a case where the V/III ratio is a predetermined value in the rangefrom 3000 or more to 7500 or less, the formation is made such that theinterface between the channel layer 3 and the barrier layer 5 has a meanroughness in the range from 0.1 nm to 1 nm and the surface of thebarrier layer 5 has a mean square roughness in the range from 0.1 nm tonm in a field of view of 5 μm×5 μm.

Here, the barrier layer formation temperature T2 is in the range from650° C. or more to 800° C. or less, and in a temperature range of800−667·x2(° C.)≦T2≦860−667·x2(° C.), which is determined in accordancewith an InN mole fraction x2 in the barrier layer 5.

FIG. 6 is a diagram for explaining that the harrier layer formationtemperature T2 is determined in the above-mentioned temperature range.That is, FIG. 6 is a diagram plotting the InN mole fraction x2 in thebarrier layer 5 against the temperature of the susceptor, in a casewhere a ratio (hereinafter, In flow ratio) of the flow rate of the Insource gas to the flow rate of the entire metal organic source gas isvaried within the range from 0.5 or more to 0.8 or less, and thetemperature of the susceptor (corresponding to the barrier layerformation temperature T2) at a time when the barrier layer 5 is formedis varied. The V/III ratio is set to be 5000.

FIG. 6 reveals that data points are positioned on substantially the samestraight line irrespective of the In flow ratio. This indicates thatthere is substantially a linear function relationship between thebarrier layer formation temperature T2 and the InN mole fraction x2.Since there is no dependence on the In flow ratio, it is concluded thatthe InN mole fraction of the barrier layer is controllable by thebarrier layer formation temperature T2 (the temperature of thesusceptor) according to the above-mentioned functional relationship.That is, the barrier layer 5 having an aimed composition can be formed.

More specifically, from a state of arrangement of the data points inFIG. 6, a regression line represented by the following expression isderived.

T2=830−667·x2

Accordingly, in principle, if a desired InN mole fraction x2 isdetermined, the barrier layer formation temperature T2 can be determinedfrom the above expression. Even in consideration of a variation causedby a difference among individual MOCVD apparatuses or individual heatingmembers used for heating, the barrier layer 5 having a desired InN molefraction x2 can be formed without fail by selecting a suitabletemperature in a range of ±30° C. from the above expression. That is,when the relationship of 800−667·x2(° C.)≦T2≦860−667·x2 (° C.) issatisfied, the barrier layer 5 can be formed so as to have excellentcontrollability in a wide composition range, for example, in thecomposition range determined by the above-mentioned expressions (1) to(4).

Moreover, in this embodiment, for the preparation of the barrier layer5, a nitrogen gas is used for all of a bubbling gas of a metal organicsource and a carrier gas. That is, an atmosphere gas other than thesource gas is only the nitrogen gas. Accordingly, thehydrogen-terminated dangling bond can be made nitrogen-terminated, andan electron structure of the barrier layer 5 is maintained in an idealstate, with the result that the generation of the two-dimensionalelectron gas in the two-dimensional electron gas region 3 e is achievedwith a high concentration. Note that it is not preferable tointentionally mix a hydrogen gas into the atmosphere during thepreparation of the barrier layer 5, because this causes a reduction inthe two-dimensional electron gas concentration.

After the formation of the In_(x2)Al_(y2)Ga_(z2)N layer, then thetemperature of the susceptor is set to be a predetermined sub insulatinglayer formation temperature. In this condition, an Al source gas and aNH₃ gas are introduced into the reactor, and thereby an AlN layerserving as the sub insulating layer 6 b is formed with a predeterminedthickness.

After the formation of the AlN layer, then the temperature of thesusceptor is set to be a main insulating layer formation temperaturethat is 750° C. or more and 850° C. or less (for example, 800° C.). Inthis condition, a silane gas and a NH₃ gas are introduced into thereactor, and thereby a silicon nitride layer serving as the maininsulating layer 6 a is formed with a predetermined thickness.

Here, as described above, the main insulating layer formationtemperature is set lower than an ordinary formation temperature that isadopted in a case where a silicon nitride layer is provided as aninsulating layer. Forming the main insulating layer 6 a at a temperaturehigher than 850° C. is not preferable, because this increases a contactresistance of the HEMT device 20. On the other hand, setting the maininsulating layer formation temperature to be below 750° C. is notpreferable, because this makes it difficult to form the main insulatinglayer 6 a itself through a MOCVD process.

Upon the formation of the main insulating layer 6 a, the preparation ofthe epitaxial substrate 10 is completed. After the epitaxial substrate10 is obtained, this is used to prepare the HEMT device 20. Subsequentsteps are achieved through a known method.

Firstly, a device isolation step is performed for etching and removingportions that will be boundaries between individual devices through aphotolithography process and an RIE process into a depth of about 400nm. This device isolation step is a step necessary for obtaining a largenumber of HEMT devices 20 from one epitaxial substrate 10, andessentially not necessary for the present invention.

After the device isolation step is performed, a SiO₂ film having apredetermined thickness (for example, 10 nm) is formed on the epitaxialsubstrate 10. Then, through a photolithography process, the SiO₂ filmonly in expected formation positions where the source electrode 7 andthe drain electrode 8 are to be formed is removed by etching. Thereby, aSiO₂ pattern layer is formed.

After the formation of the SiO₂ pattern layer, through a vacuum vapordeposition process and a photolithography process, the source electrode7 and the drain electrode 8 made of Ti/Al/Ni/Au are formed at theirexpected formation positions. Then, a heat treatment is performed forseveral tens of seconds (for example, 30 seconds) in the nitrogen gasatmosphere at a predetermined temperature (for example, 800° C.) in therange from 650° C. to 1000° C. As a result of this heat treatment, metalelements of the electrodes are alloyed, and diffused to transmit throughthe main insulating layer 6 a. This ensures suitable ohmiccharacteristics of the source electrode 7 and the drain electrode 8relative to the barrier layer 5.

After the heat treatment, the SiO₂ film in an expected formationposition where the gate electrode 9 is to be formed is removed from theSiO₂ pattern layer through a photolithography process. Then, through avacuum vapor deposition process and a photolithography process, the gateelectrode 9 made of Ni/Au is formed in this expected formation position.The gate electrode 9 is formed as a Schottky metal pattern.

Then, through a photolithography process, the remaining portion of theSiO₂ pattern layer is removed. Then, a resultant is singulated intochips each having a predetermined size. Thereby, a large number of HEMTdevices 20 are obtained. On the HEMT device 20 thus obtained, diebonding and wire bonding are performed as appropriate.

It may be possible that, prior to making the chips, the HEMT device 20thus obtained is subjected to a heat treatment for the purpose ofimproving a mechanical strength of a bonding portion between the gateelectrode 9 and the epitaxial substrate 10 (for the purpose ofpreventing peeling of the gate electrode 9). In one preferred example,this heat treatment is performed by holding the HEMT device 20 forseveral tens of seconds in a nitrogen gas atmosphere at a predeterminedtemperature in the range from 500° C. to 900° C.

<Features of Epitaxial Substrate and HEMT Device>

Next, features of the epitaxial substrate 10 and the HEMT device 20having the above-described configuration will be described.

Firstly, the epitaxial substrate 10 according to this embodiment, inwhich the compositions of the channel layer 3 and the barrier layer 5are determined in the above-mentioned composition ranges, is structuredsuch that it is less influenced by a surface level and such that aspontaneous polarization effect makes more contribution than a piezoeffect. Moreover, the inventors has confirmed that, as compared with astructure (AlGaN/GaN structure) in which the channel layer 3 is made ofGaN and the barrier layer is made of AlGaN, a high two-dimensionalelectron gas concentration is maintained and a sheet resistance is keptlow, even when the thickness of the barrier layer is reduced.

Additionally, in the epitaxial substrate 10, the main insulating layer 6a is formed in the above-described manner, and therefore a surface levelis controlled. This exerts effects that a high two-dimensional electrongas concentration is maintained and the sheet resistance is furtherreduced. For example, in the epitaxial substrate 10, the sheetresistance is reduced down to about ½, as compared with a case where nomain insulating layer 6 a is provided.

It is generally considered that a substrate having a hightwo-dimensional electron gas concentration and a low resistance is notsuited for an HEMT device of normally-off operation type. However, inthe epitaxial substrate 10 according to this embodiment, both thethickness of the barrier layer 5 and the thickness of the maininsulating layer 6 a are 3 nm or less, but nevertheless a hightwo-dimensional electron gas concentration and a low sheet resistanceare maintained. Therefore, in the HEMT device 20 prepared by using theepitaxial substrate 10, a normally-off state is achieved only by abuilt-in potential of a portion corresponding to the gate electrode 9.The following fact also contributes to the achievement of thenormally-off state. That is, the main insulating layer 6 a made ofsilicon nitride is bonded to the barrier layer 5 with a sufficientlysmall thickness made of a group-III nitride having a composition ofIn_(x2)Al_(y2)Ga_(z2)N, so that a conduction hand edge of the barrierlayer 5 is, throughout the entire film thickness thereof, pushed uptoward a high energy side.

There is a tendency that increasing the thickness of the main insulatinglayer 6 a reduces a threshold voltage. When the thickness is greaterthan 3 nm, the threshold voltage is negative, so that the normally-offoperation is not achieved.

As described above, in this embodiment, the main insulating layer 6 a isformed as a layer with a low crystallinity. This exerts an effect that,in the heat treatment performed after the formation of the pattern ofthe source electrode 7 and the drain electrode 8, the diffusion andtransmission of metal elements of these electrodes in the maininsulating layer 6 a is suitably provoked. In the HEMT device 20, eventhough the source electrode 7 and the drain electrode 8 are formed onthe main insulating layer 6 a, the ohmic characteristics of theseelectrodes are sufficiently ensured. As a result, the contact resistanceis suppressed. For example, a contact resistance of an epitaxialsubstrate whose main insulating layer 6 a is formed at 900° C. is twoorders higher than the contact resistance of the epitaxial substrate 10according to this embodiment whose main insulating layer 6 a is formedat a temperature in the range from 750° C. to 850° C.

Providing the sub insulating layer 6 b in addition to the maininsulating layer 6 a exerts an effect that the gate leakage current isreduced in the HEMT device 20. However, a thickness equal to or greaterthan 3 nm is not preferable, because it causes the threshold voltage tobe negative, thus failing to achieve the normally-off operation, and italso increases the contact resistance.

The HEMT device 20 according to this embodiment has the MIS gatestructure. This can ensure a higher upper limit of a gate voltage range,as compared with a HEMT device of Schottky type in which an upper limitof the gate positive voltage is limited by the height of the Schottkybarrier. That is, the gate voltage range can be enlarged as comparedwith the HEMT device of Schottky type. As a result, a drain current canbe increased. Additionally, a gate junction is substantially an MISjunction, and therefore the leakage current is reduced in both caseswhere the gate bias is positive and negative.

From another viewpoint, it is considered that this embodiment achievesan HEMT device of normally-off operation type having excellentcharacteristics without performing a troublesome step of forming arecess gate structure. This does not exclude that the source electrode 7and the drain electrode 8 have recess structures.

Furthermore, the main insulating layer 6 a made of silicon nitride isformed continuously from the layer (the sub insulating layer 6 b or thebarrier layer 5) located immediately below. Therefore, a reduction indrain-current collapse, and the like, are expected.

As thus far described, in this embodiment, a barrier layer is formedwith a thickness of 3 nm or less so as to satisfy the above-mentionedcomposition range, and a (main) insulating layer made of silicon nitrideis formed with a thickness of 3 nm or less at a formation temperature of750° C. to 850° C. Thereby, an epitaxial substrate having a hightwo-dimensional electron concentration and a low sheet resistance isachieved.

By using such an epitaxial substrate, an HEMT device of normally-offoperation type having a low on-resistance, in which the gate thresholdvoltage has a positive value and the upper limit of the gate voltage ishigh, can be achieved without performing a troublesome step of forming arecess gate structure.

EXAMPLES Example 1

In this example, as the epitaxial substrate 10 according to theabove-described embodiment, 36 types of epitaxial substrates 10 wereprepared which were common to one another in terms of the compositionsof the channel layer 3 and the barrier layer 5 and different from oneanother in terms of the combination of four preparation conditions,namely, the thickness of the barrier layer 5, the thickness of the maininsulating layer 6 a, the formation temperature (the temperature of thesusceptor) at which the main insulating layer 6 a was formed, and thethickness of the sub insulating layer 6 b. Then, each of the types ofepitaxial substrates 10 thus obtained was measured for its sheetresistance. Moreover, each epitaxial substrate 10 was used to prepare anHEMT device 20, and its threshold voltage, contact resistance, and gateleakage current were evaluated. Table 1 shows a list of formationconditions specific to and measurement results of specimens (specimenNos. a-1 to a-18) in which the channel layer 3 was made of GaN and thebarrier layer 5 was made of In_(0.23)Al_(0.77)N. Table 2 shows a list offormation conditions specific to and measurement results of specimens(specimen Nos. b-1 to b-18) in which the channel layer 3 is made ofAl_(0.2)Ga_(0.8)N and the barrier layer 5 is made ofIn_(0.154)Al_(0.646)Ga_(0.2)N.

Firstly, the epitaxial substrate 10 was prepared. At that time, untilthe formation of the barrier layer 5, all the epitaxial substrates 10were prepared under the same conditions except the above-mentionedconditions.

To be specific, firstly, a plurality of (0001)-oriented 6H—SiCsubstrates having a diameter of two inches were prepared as the basesubstrate 1. The thickness thereof was 300 μm. Each of the substrateswas placed in a reactor of an MOCVD apparatus, and the inside of thereactor was vacuumed. Then, the pressure in the reactor was set to be 30kPa, and an atmosphere in a hydrogen/nitrogen mixed flow state wascreated. Then, the susceptor was heated, to thereby raise thetemperature of the base substrate 1.

After the temperature of the susceptor reached 1050° C., a TMA bubblinggas and an ammonia gas were introduced into the reactor, and an AlNlayer having a thickness of 200 nm was formed as the buffer layer.

Then, the temperature of the susceptor was set to be a predeterminedtemperature, a TMG bubbling gas serving as the metal organic source gasand an ammonia gas were introduced into the reactor with a predeterminedflow ratio. Thus, a GaN layer or Al_(0.2)Ga_(0.8)N layer serving as thechannel layer 3 was formed with a thickness of 2 μm).

After the formation of the channel layer 3, the pressure in the reactorwas set to be 10 kPa, and then a TMA bubbling gas and an ammonia gaswere introduced into the reactor. Thus, an AlN layer having a thicknessof 1 nm was formed as the spacer layer 4.

After the formation of the spacer layer 4, the barrier layer 5 was thenformed. The temperature of the susceptor was set in accordance with thecomposition of the barrier layer. The thickness of the barrier layer 5was varied in four levels of 2 nm, 2.5 nm, 3 nm, and 4 nm.

After the formation of the barrier layer 5, in part of the specimens, anAlN layer serving as the sub insulating layer 6 b was formed. Thethickness of the sub insulating layer 6 b was varied in five levels of 0nm (corresponding to a case where no sub insulating layer 6 b isprovided), 1 nm, 2 nm, 2.5 nm, and 3 nm. In any of the cases, thetemperature of the susceptor was 1050° C.

Then, in the specimens with the exception of a part of them, a siliconnitride layer serving as the main insulating layer 6 a was formed. Thethickness of the main insulating layer 6 a was varied in six levels of 0nm (corresponding to a case where no main insulating layer 6 a isprovided), 1.5 nm, 2 nm, 2.5 nm, 3 nm, and 4 nm. The temperature of thesusceptor was varied in five levels of 750° C., 800° C., 850° C., 900°C., and 1000° C.

After all the intended layers were formed, the temperature of thesusceptor was lowered to the vicinity of a room temperature, and theinside of the reactor was returned to the atmospheric pressure. Then,the prepared epitaxial substrates 10 were taken out. Through theabove-described procedures, each of the epitaxial substrates 10 wasobtained.

The obtained epitaxial substrates 10 were measured for their sheetresistances by the four-terminal method. The results thus obtained wereshown in Table 1 and Table 2.

Then, through a photolithography process and a vacuum vapor depositionprocess, an electrode pattern made of Ti/Al/Ni/Au (with film thicknessesof 25/75/15/100 nm, respectively) was formed on an upper surface of themain insulating layer 6 a in expected formation positions where thesource electrode 7 and the drain electrode 8 were to be formed. Then, aheat treatment was performed in nitrogen for 30 seconds at 800° C.

Then, through a photolithography process and a vacuum vapor depositionprocess, a pattern of the gate electrode 9 made of Ni/Au (with a filmthickness of 6 nm/12 nm) was formed on the upper surface of the maininsulating layer 6 a in an expected formation position where the gateelectrode 9 was to be formed. The gate electrode 9 was formed such thatits portion bonded to the main insulating layer 6 a has a size of 1 mm×1mm.

Finally, a resultant was singulated into chips, thus obtaining a largenumber of HEMT devices 20.

Die bonding and wire bonding were performed on the obtained HEMT devices20, and then, by the Hall effect method, the threshold voltage, thecontact resistance, and the gate leakage current caused upon applicationof −100V, were measured. Results thereof are shown in Table 1 and Table2.

TABLE 1 Film Gate Leakage Film Main Insulating Layer Thickness ofCurrent Thickness Film Formation Sub Sheet Threshold Contact (when −100V of Barrier Thickness Temperature Insulating Resistance VoltageResistance was applied) No. Layer (nm) (nm) (° C.) Layer (nm) (Ω · sq)(V) (Ω · cm²) (A/mm) Evaluation a-1 2 0 — 0 860 1.20 7.5E−06 1.2E−04OUTSIDE SCOPE OF PRESENT INVENTION a-2 2 1.5 800 0 420 0.75 7.2E−063.5E−08 a-3 2 2 800 0 414 0.64 6.3E−06 4.0E−09 a-4 2 2 800 0 413 0.645.5E−06 4.0E−09 a-5 2 2.5 800 0 425 0.50 6.0E−06 1.6E−10 a-6 2 3 800 0416 0.25 8.0E−06 5.6E−10 a-7 2 4 800 0 418 −0.16 6.5E−06 4.3E−09 OUTSIDESCOPE OF PRESENT INVENTION a-8 2 2 750 0 418 0.65 5.0E−06 4.2E−08 a-9 22 850 0 416 0.64 6.0E−06 3.5E−09 a-10 2 2 900 0 416 0.60 1.2E−04 2.4E−09OUTSIDE SCOPE OF PRESENT INVENTION a-11 2 2 1000 0 419 0.60 5.5E−041.2E−09 OUTSIDE SCOPE OF PRESENT INVENTION a-12 2.5 2 800 0 420 0.485.8E−06 4.2E−09 a-13 3 2 800 0 418 0.31 7.0E−06 5.0E−09 a-14 4 2 800 0422 −0.20 7.0E−06 4.4E−09 OUTSIDE SCOPE OF PRESENT INVENTION a-15 2 2800 1 421 0.45 7.2E−06 4.0E−10 a-16 2 2 800 2 418 0.30 9.3E−06 2.0E−10a-17 2 2 800 2.5 416 0.10 1.2E−05 1.5E−10 a-18 2 2 800 3 419 −0.406.5E−04 1.2E−10 OUTSIDE SCOPE OF PRESENT INVENTION

TABLE 2 Film Gate Leakage Film Main Insulating Layer Thickness ofCurrent Thickness Film Formation Sub Sheet Threshold Contact (when −100V of Barrier Thickness Temperature Insulating Resistance VoltageResistance was applied) No. Layer (nm) (nm) (° C.) Layer (nm) (Ω · sq)(V) (Ω · cm²) (A/mm) Evaluation b-1 2 0 — 0 980 1.44 8.0E−06 1.1E−04OUTSIDE SCOPE OF PRESENT INVENTION b-2 2 1.5 800 0 580 0.99 5.0E−063.3E−08 b-3 2 2 800 0 574 0.89 8.8E−06 3.8E−09 b-4 2 2 800 0 575 0.886.0E−06 3.8E−09 b-5 2 2.5 800 0 565 0.74 7.0E−06 1.5E−10 b-6 2 3 800 0574 0.49 8.0E−06 5.3E−10 b-7 2 4 800 0 574 −0.03 8.5E−06 4.1E−09 OUTSIDESCOPE OF PRESENT INVENTION b-8 2 2 750 0 571 0.89 8.5E−06 4.0E−08 b-9 22 850 0 572 0.88 6.0E−06 3.3E−09 b-10 2 2 900 0 573 0.84 2.4E−04 2.3E−09OUTSIDE SCOPE OF PRESENT INVENTION b-11 2 2 1000 0 575 0.84 7.5E−041.1E−09 OUTSIDE SCOPE OF PRESENT INVENTION b-12 2.5 2 800 0 573 0.729.0E−06 4.0E−09 b-13 3 2 800 0 570 0.55 8.0E−06 4.8E−09 b-14 4 2 800 0580 −0.02 9.0E−06 4.2E−09 OUISIDE SCOPE OF PRESENT INVENTION b-15 2 2800 1 579 0.60 8.0E−06 7.8E−10 b-16 2 2 800 2 581 0.25 9.0E−06 5.0E−10b-17 2 2 800 2.5 572 0.05 1.4E−05 3.4E−10 b-18 2 2 800 3 577 −0.258.0E−04 1.5E−10 OUTSIDE SCOPE OF PRESENT INVENTION

The results shown in Table 1 and Table 2 reveal that the sheetresistances of the specimens (a-2 to a-18, b-2 to b-18) including themain insulating layer 6 a were reduced to about ½ of the sheetresistances of the specimens (a-1, b-1) not including the maininsulating layer 6 a. This indicates that providing the main insulatinglayer 6 a is effective in a reduction in the sheet resistance of theepitaxial substrate 10.

Moreover, the gate leakage currents of the specimens including the maininsulating layer 6 a were reduced to about 1/10000 to 1/1000000 of thegate leakage currents of the specimens not including the main insulatinglayer 6 a. This indicates that preparing the HEMT device 20 by using theepitaxial substrate 10 that includes the main insulating layer 6 a ishighly effective in a reduction in the gate leakage current of the HEMTdevice 20.

Focusing on the relationship of the characteristics of the HEMT device20 relative to the thicknesses of the barrier layer 5 and the maininsulating layer 6 a, there is a tendency that, as each of thethicknesses increases, the threshold voltage decreases. When thethickness was 3 nm or less, the threshold voltage had a positive value,while only the specimens (a-7, a-14, b-7, b-14) with a thickness of 4 nmhad negative threshold voltages. This result indicates that, in order toachieve the HEMT device 20 of normally-off operation type, it isnecessary that both of the thicknesses of the barrier layer 5 and themain insulating layer 6 a are set to be 3 nm or less. When the thresholdvoltage is in a positive range, there is a tendency that, as thethickness of the main insulating layer 6 a increases, the gate leakagecurrent decreases.

Focusing on the relationship of the characteristics of the HEMT device20 and the formation temperature at which the main insulating layer 6 awas formed, the contact resistances of the specimens (a-10, a-11, b-10,b-11) having a formation temperature of 900° C. or more were about twoorders higher than the contact resistances of the other specimens havinga formation temperature of 800° C. or less. This result indicates thatlowering the formation temperature to thereby form the main insulatinglayer 6 a as a layer having a lower crystallinity than that of anordinary insulating layer is effective in a reduction in the contactresistance.

Moreover, focusing on the specimens (a-15 to a-18, b-15 to b-18)including the sub insulating layer 6 b, the gate leakage currentsthereof were lower than the gate leakage currents of the specimens (a-3,a-4, b-3, b-4) not including the sub insulating layer 6 b in which thebarrier layer 5 and the main insulating layer 6 a were prepared underthe same preparation conditions. However, in the specimens (a-18, b-18)in which the sub insulating layer 6 b had a thickness of 4 nm, thethreshold voltages were negative and the contact resistances wereincreased. This result means that providing the sub insulating layer 6 bwith a thickness of 3 nm or less is effective in a reduction in the gateleakage current of the HEMT device 20. Here, there is a tendency that,as the thickness of the sub insulating layer 6 b increases, thethreshold voltage decreases. Therefore, in order to achieve thenormally-off operation without fail, it would be preferable that thethickness of the sub insulating layer 6 b is 2 nm or less.

Example 2

In this example, as the epitaxial substrate 10 according to theabove-described embodiment, 28 types of epitaxial substrates 10 wereprepared under the same conditions as in the example 1 except that thecomposition of the channel layer 3 was varied in four levels and thecomposition of the barrier layer 5 was varied in seven levels. Then,each of the types of epitaxial substrates 10 thus obtained was measuredfor its sheet resistance. Moreover, each epitaxial substrate 10 was usedto prepare an HEMT device 20, and its threshold voltage, contactresistance, and gate leakage current were evaluated. In all thespecimens (specimen Nos. c-1 to c-18), the thickness of the barrierlayer 5 was 2 nm. The thickness of the main insulating layer 6 a was 2nm and the formation temperature (the temperature of the susceptor) atwhich the main insulating layer 6 a was formed was 800° C. The subinsulating layer 6 b was not formed. Table 3 shows a list of formationconditions specific to and measurement results of the specimens.

In the ternary phase diagrams for three components of InN, AlN, and GaNshown in FIGS. 2 to 5, the compositions of the barrier layers 5 of therespective specimens were plotted with circles. That is, thecompositions of the channel layers 3 and the barrier layers 5 of all thespecimens were including in a range that is enclosed by four straightlines represented by the expressions (1) to (4).

TABLE 3 Gate Leakage Composition Composition of Barrier Sheet ThresholdContact Current of Channel Layer Resistance Voltage Resistance (when−100 V was No. Layer In_(x2) Al_(y2) Ga_(z2) (Ω · sq) (V) (Ω · cm²)applied) (A/mm) c-1 GaN 0.25 0.75 0 591 0.99 9.0E−06 5.0E−09 c-2 0.230.77 0 414 0.64 6.3E−06 4.0E−09 c-3 0.21 0.79 0 301 0.30 4.6E−06 3.5E−09c-4 0.19 0.61 0.2 607 1.00 9.3E−06 5.4E−09 c-5 0.16 0.64 0.2 371 0.535.7E−06 6.5E−09 c-6 0.11 0.49 0.4 514 0.82 7.8E−06 5.5E−09 c-7 0.08 0.520.4 325 0.39 5.0E−06 5.8E−09 c-8 Al_(0.1)Ga_(0.9)N 0.232 0.768 0 5460.93 8.3E−06 8.0E−09 c-9 0.212 0.788 0 391 0.59 6.0E−06 5.1E−09 c-100.192 0.808 0 288 0.24 4.4E−06 6.0E−09 c-11 0.172 0.628 0.2 558 0.958.5E−06 5.5E−09 c-12 0.142 0.658 0.2 352 0.48 5.4E−06 4.5E−09 c-13 0.0920.508 0.4 478 0.76 7.3E−06 7.3E−09 c-14 0.062 0.538 0.4 310 0.34 4.7E−065.5E−09 c-15 Al_(0.2)Ga_(0.8)N 0.214 0.786 0 561 0.88 8.6E−06 6.0E−09c-16 0.194 0.806 0 370 0.53 5.7E−06 5.2E−09 c-17 0.174 0.826 0 277 0.194.2E−05 6.3E−09 c-18 0.154 0.646 0.2 574 0.89 8.8E−06 3.8E−09 c-19 0.1240.676 0.2 335 0.43 5.1E−06 4.5E−08 c-20 0.074 0.526 0.4 446 0.71 6.8E−067.1E−09 c-21 0.044 0.556 0.4 296 0.28 4.5E−06 6.1E−09 c-22Al_(0.3)Ga_(0.7)N 0.196 0.804 0 520 0.83 7.9E−06 5.4E−09 c-23 0.1760.824 0 352 0.48 5.4E−06 6.3E−09 c-24 0.156 0.844 0 266 0.13 4.1E−066.6E−09 c-25 0.136 0.664 0.2 531 0.84 8.1E−06 7.2E−08 c-26 0.106 0.6940.2 319 0.37 4.9E−06 4.8E−09 c-27 0.056 0.544 0.4 419 0.65 6.4E−064.4E−09 c-28 0.026 0.574 0.4 284 0.22 4.3E−06 5.6E−09

The results shown in Table 3 indicate that preparing an epitaxialsubstrate by selecting the compositions of the channel layer 3 and thebarrier layer 5 from the composition ranges represented by theexpressions (1) to (4) can achieve an epitaxial substrate having a lowsheet resistance, and that preparing an HEMT device by using thisepitaxial substrate as described in the embodiment above can achieve anHEMT device of normally-off operation type having a low on-resistance inwhich the gate threshold voltage has a positive value and the upperlimit of the gate voltage is high.

1. An epitaxial substrate for semiconductor device, comprising a basesubstrate; a channel layer made of a first group-III nitride having acomposition of In_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1) that contains atleast Al and Ga; and a barrier layer made of a second group-III nitridehaving a composition of In_(x2)Al_(y2)Ga_(z2)N (x2+y2+z2=1) thatcontains at least In and Al, wherein the composition of said firstgroup-III nitride is in a range determined by x1=0 and 0≦y1≦0.3, thecomposition of said second group-III nitride is, in a ternary phasediagram for InN, AlN, and GaN, in a range that is enclosed by straightlines represented by the following expressions and that is determined inaccordance with the composition of said first group-III nitride, saidbarrier layer has a thickness of 3 nm or less, a low-crystallinityinsulating layer is formed on said barrier layer, said low-crystallinityinsulating layer being made of silicon nitride and having a thickness of3 nm or less.${x\; 2} = {\frac{{y\; 2} - \left( {0.27 + {0.5{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.73 - {0.5{yl}}} \right)}{2.78}}}$${x\; 2} = {\frac{{y\; 2} - \left( {0.4 + {0.6{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.6 - {0.6{yl}}} \right)}{2.78}}}$z2=0.4z2=0
 2. The epitaxial substrate for semiconductor device according toclaim 1, further comprising: a sub insulating layer provided betweensaid barrier layer and said low-crystallinity insulating layer, said subinsulating layer being made of a group-III nitride with insulatingproperties and having a thickness of 2.5 nm or less.
 3. The epitaxialsubstrate for semiconductor device according to claim 2, wherein saidsub insulating layer is made of AlN.
 4. The epitaxial substrate forsemiconductor device according to claim 1, further comprising: a spacerlayer provided between said channel layer and said barrier layer, saidspacer layer being made of a third group-III nitride having acomposition of In_(x3)Al_(y3)Ga_(z3)N (x3+y3+z3=1) that contains atleast Al and that has higher band gap energy than that of said barrierlayer, wherein a total thickness of said spacer layer and said barrierlayer is 5 nm or less.
 5. The epitaxial substrate for semiconductordevice according to claim 4, wherein said spacer layer is made of AlN.6. A semiconductor device, comprising: a base substrate; a channel layermade of a first group-III nitride having a composition ofIn_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1) that contains at least Al and Ga;and a barrier layer made of a second group-III nitride having acomposition of In_(x2)Al_(y2)Ga_(z2)N (x2+y2+z2=1) that contains atleast In and Al, wherein the composition of said first group-III nitrideis in a range determined by x1=0 and 0≦y1≦0.3, the composition of saidsecond group-III nitride is, in a ternary phase diagram for InN, AlN,and GaN, in a range that is enclosed by straight lines represented bythe following expressions and that is determined in accordance with thecomposition of said first group-III nitride, said barrier layer has athickness of 3 nm or less, a low-crystallinity insulating layer isformed on said barrier layer, said low-crystallinity insulating layerbeing made of silicon nitride and having a thickness of 3 nm or less, asource electrode and a drain electrode are formed on saidlow-crystallinity insulating layer with an ohmic junction, and a gateelectrode is formed on said low-crystallinity insulating layer with aSchottky junction.${x\; 2} = {\frac{{y\; 2} - \left( {0.27 + {0.5{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.73 - {0.5{yl}}} \right)}{2.78}}}$${x\; 2} = {\frac{{y\; 2} - \left( {0.4 + {0.6{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.6 - {0.6{yl}}} \right)}{2.78}}}$z2=0.4z2=0
 7. A method of manufacturing a epitaxial substrate forsemiconductor device, said method comprising: a channel layer formationstep of epitaxially forming a channel layer on a base substrate, saidchannel layer being made of a first group-III nitride having acomposition of In_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1) that contains atleast Al and Ga; a barrier layer formation step of epitaxially forming abarrier layer on said channel layer, said barrier layer being made of asecond group-III nitride having a composition of In_(x2)Al_(y2)Ga_(z2)N(x2+y2+z2=1) that contains at least In and Al; and a main insulatinglayer formation step of forming a main insulating layer on said barrierlayer, said main insulating layer being made of silicon nitride, whereinin said channel layer formation step, the composition of said firstgroup-III nitride is selected from a range determined by x1=0 and0≦y1≦0.3, in said barrier layer formation step, the composition of saidsecond group-III nitride is selected from a range that is enclosed bystraight lines represented by the following expressions and that isdetermined in accordance with the composition of said first group-IIInitride in a ternary phase diagram for InN, AlN, and GaN, and saidbarrier layer is formed with a thickness of 3 nm or less, in said maininsulating layer formation step, said main insulating layer is formedwith a thickness of 3 nm or less at a formation temperature of 750° C.or more and 850° C. or less.${x\; 2} = {\frac{{y\; 2} - \left( {0.27 + {0.5{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.73 - {0.5{yl}}} \right)}{2.78}}}$${x\; 2} = {\frac{{y\; 2} - \left( {0.4 + {0.6{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.6 - {0.6{yl}}} \right)}{2.78}}}$z2=0.4z2=0
 8. The method of manufacturing an epitaxial substrate forsemiconductor device according to claim 7, further comprising: a subinsulating layer formation step of forming a sub insulating layer onsaid barrier layer, said sub insulating layer being made of a group-IIInitride with insulating properties and having a thickness of 2.5 nm orless, wherein said main insulating layer is formed on said subinsulating layer.
 9. The method of manufacturing an epitaxial substratefor semiconductor device according to claim 8, wherein said subinsulating layer is made of AlN.
 10. The method of manufacturing anepitaxial substrate for semiconductor device according to claim 7,further comprising: a spacer layer formation step of forming a spacerlayer on said channel layer, said spacer layer being made of a thirdgroup-III nitride having a composition of In_(x3)Al_(y3)Ga_(z3)N(x3+y3+z3=1) that contains at least Al and that has higher band gapenergy than that of said barrier layer, wherein said barrier layer isformed on said spacer layer.
 11. The method of manufacturing anepitaxial substrate for semiconductor device according to claim 10,wherein said spacer layer is made of AlN.
 12. The method ofmanufacturing an epitaxial substrate for semiconductor device accordingto claim 7, wherein a temperature T1(° C.) at which said channel layeris formed is determined within a range of 950° C.≦T1≦1250° C., atemperature T2(° C.) at which said barrier layer is formed is determinedwithin a range of 800−667·x2(° C.)≦T2≦860−667·x2(° C.) and 600°C.≦T2≦850° C., said range being determined in accordance with an InNmole fraction x2 in said second group-III nitride.
 13. A method ofmanufacturing a semiconductor device, said method comprising the stepsof: preparing an epitaxial substrate with following steps, a channellayer formation step of epitaxially forming a channel layer on a basesubstrate, said channel layer being made of a first group-III nitridehaving a composition of In_(x1)Al_(y1)Ga_(z1)N (x1+y1+z1=1) thatcontains at least Al and Ga, a barrier layer formation step ofepitaxially forming a barrier layer on said channel layer, said barrierlayer being made of a second group-TIT nitride having a composition ofIn_(x2)Al_(y2)Ga_(z2)N (x2+y2+z2=1) that contains at least In and Al,and a main insulating layer formation step of forming a main insulatinglayer on said barrier layer, said main insulating layer being made ofsilicon nitride, wherein in said channel layer formation step, thecomposition of said first group-III nitride is selected from a rangedetermined by x1=0 and 0≦y1≦0.3, in said barrier layer formation step,the composition of said second group-III nitride is selected from arange that is enclosed by straight lines represented by the followingexpressions and that is determined in accordance with the composition ofsaid first group-III nitride in a ternary phase diagram for InN, AlN,and GaN, and said barrier layer is formed with a thickness of 3 nm orless, in said main insulating layer formation step, said main insulatinglayer is formed with a thickness of 3 nm or less at a formationtemperature of 750° C. or more and 850° C. or less; forming a sourceelectrode and a drain electrode on said main insulating layer of saidepitaxial substrate, with an ohmic junction; performing a heat treatmenton said epitaxial substrate having said source electrode and said drainelectrode formed thereon; and forming a gate electrode on said maininsulating layer, with a Schottky junction.${x\; 2} = {\frac{{y\; 2} - \left( {0.27 + {0.5{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.73 - {0.5{yl}}} \right)}{2.78}}}$${x\; 2} = {\frac{{y\; 2} - \left( {0.4 + {0.6{yl}}} \right)}{1.78} = {- \frac{{z\; 2} - \left( {0.6 - {0.6{yl}}} \right)}{2.78}}}$z2=0.4z2=0
 14. The epitaxial substrate for semiconductor device according toclaim 2, further comprising: a spacer layer provided between saidchannel layer and said barrier layer, said spacer layer being made of athird group-III nitride having a composition of In_(x3)Al_(y3)Ga_(z3)N(x3+y3+z3=1) that contains at least Al and that has higher band gapenergy than that of said barrier layer, wherein a total thickness ofsaid spacer layer and said barrier layer is 5 nm or less.
 15. Theepitaxial substrate for semiconductor device according to claim 14,wherein said spacer layer is made of AlN.
 16. The method ofmanufacturing an epitaxial substrate for semiconductor device accordingto claim 8, further comprising: a spacer layer formation step of forminga spacer layer on said channel layer, said spacer layer being made of athird group-III nitride having a composition of In_(x3)Al_(y3)Ga_(z3)N(x3+y3+z3=1) that contains at least Al and that has higher band gapenergy than that of said barrier layer, wherein said barrier layer isformed on said spacer layer.
 17. The method of manufacturing anepitaxial substrate for semiconductor device according to claim 16,wherein said spacer layer is made of AlN.
 18. The method ofmanufacturing an epitaxial substrate for semiconductor device accordingto claim 8, wherein a temperature T1(° C.) at which said channel layeris formed is determined within a range of 950° C.≦T1≦1250° C., atemperature T2(° C.) at which said barrier layer is formed is determinedwithin a range of 800−667·x2(° C.)≦T2≦860−667·x2(° C.) and 600°C.≦T2≦850° C., said range being determined in accordance with an InNmole fraction x2 in said second group-III nitride.